1. Field
One embodiment of the invention relates to the improvement of an error correcting apparatus and an error correcting method which subject a digital information sequence to an error correction encoding process.
2. Description of the Related Art
As is commonly known, in a system which records and reproduces digital information sequences corresponding to, for example, pictures and sounds onto and from an information recording medium, such as a disk or tape, ECC (error correcting code) parity is added to a digital information sequence to be recorded and then a modulation process for satisfying the request of the recording and reproducing system, such as the process of preventing zeros from running for more than a specific length is carried out.
In recent years, an encoding means (sometime referred to as reverse ECC) has been developed which subjects a digital information sequence to be recorded to a first modulation process for satisfying the request of the recording and reproducing system and then subjects the added ECC parity to a second modulation process for satisfying the request of the recording and reproducing system.
However, since such an encoding means has to subject the original digital information sequence to the first modulation process and then its ECC parity to the second modulation process, that is, it has to perform two modulation processes, it has at a disadvantage in that the configuration is complicated and the number of bits in the data to be recorded increases.
Jpn. Pat. Appln. KOKAI Publication No. 2007-141341 has disclosed a method of adding a dummy bit to a digital information sequence modulated to meet the request of the recording and reproducing system, thereby generating an error correction parity bit sequence, and when the generated parity bit sequence cannot satisfy the request of the recording and reproducing system, changing the value of the dummy bit to generate a new parity bit sequence, and replacing the old sequence with the new one.
Furthermore, Jpn. Pat. Appln. KOKOKU Publication No. 3167638 has disclosed a method of, when RS (Reed-Solomon) code is used as error correction code, multiplying by a member in a Galois field instead of converting data on the basis of a modulation table, thereby giving an error correcting capability similar to the original data to the multiplication Galois field information even if the modulation circuit has only one error correction circuit.
In addition, Jpn. Pat. Appln. KOKOKU Publication No. 3827678 has disclosed a method of inserting a synchronizing code word including multiplexing information into data streams multiplexed with multiplexing information and modulating the resulting streams and selecting the one with the smallest DC component among the modulated data streams.